With the progress of the semiconductor integrated circuits to the ULSI (ultra large scale integration) levels or even higher level, the integrity of the integrated circuits rises at an amazing rate. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Taking DRAM (dynamic random access memories) for example, the increasing integrity in manufacturing extends the capacity of a single chip to step from earlier 4 megabit to 16 megabit, and further to 256 megabit or even higher. The integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed in accordance with these advancements. The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within a smaller area without influencing the characteristics and operations of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with good reliability and long operating life must be maintained without any degradation in the function. These achievements are expected to be reached with the simultaneous developments and advancements in photography, etching, deposition, ion implantation, and thermal processing technologies, the five big aspects of semiconductor manufacturing. The present technology research focus mainly on the sub-micron and one-tenth micron semiconductor devices to manufacture highly reliable and densely arranged integrated circuits.
Transistors, or more particularly the metal oxide semiconductor (MOS) transistors, are the most important and frequently employed devices among integrated circuits. However, with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanying shorter channels, problems like junction punchthrough, leakage, and the contact resistance cause the reduction in the yield and the reliability of the semiconductor manufacturing processes. Technologies like the shallow junctions are utilized in combating the undesirable effects to manufacture the densely packed devices with good yield.
The electrostatic discharge (ESD) attacking has became a serious problem as the feature size of the MOS transistors has been scaled down. A semiconductor device having the input/output pad connections with external circuitry and devices is subject to the problem of the ESD. The ESD is easily conducted through the input/output and the power lead connections into the internal devices and causes some problems to the semiconductor devices, especially serious ones like the gate oxide breakdown and damage from overheating. The high voltage gradient generated between the contacts and the channels from the ESD causes the gate oxide electron injection and the carrier acceleration effect in the channels. The characteristics and operations of the devices are easily influenced by the inducing effects of the ESD. High levels of ESD with several hundred volts to a few thousand volts, which is easily transferred to the pins of an IC package during the handling, can bring a permanent destruction to the internal devices. For preventing the devices from the ESD damage, built-in ESD protection circuits are connected between the input/output pads and the internal circuitry. A high level of abnormal discharge conducted into the pins of an IC package is kept out by the ESD protection circuits from flowing into the devices. The discharges are guided through the ESD protection circuits to the ground and the damage to the semiconductor devices is eliminated.
With the scaling down of the feature size of the MOS transistors, short channel effects are frequently presented to reduce the threshold voltage and influence the operations of the devices. Generally, the lightly doped drain (LDD) and the large-angle-tilt implant drain (LATID) technologies are widely employed to reduce the short channel effects. In the work of T. Mizlmo et al., "Hot-Carrier Effects in 0.1 .mu.m Gate Length CMOS Devices" (in IEDM Tech. Dig., p.695, 1996), the LDD structures are one of the four key technologies disclosed to realize 0.1 micrometer CMOS devices. The LDD structure are adopted to reduce both the p-n junction depth and the lateral diffusion length of the source/drain extension. The band-to-band tunneling leakage current is also suppressed. The hot-carrier effects were investigated in their work. They concluded that the hot-carrier effects in 0.1 micrometer devices are still one of the major concerns, in spite of reducing the supply voltage.
Various investigations relating to the LATID technologies have been undertaken. A 0.1 micrometer CMOS technology with tilt-implanted punchthrough stopper (TIPS) is proposed by T. Hori ("A 0.1 .mu.m CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS)", in IEDM Tech. Dig., p.75, 1994). The capability of large-angle-tilt (LAT) implant in realizing efficient punchthrough stopper pockets while keeping process compatibility is introduced in the work. They demonstrate that LAT implant can be optimized to realize sufficient punchthrough stopper pockets with suppressed bottom junction capacitance. They also propose a 0.1 micrometer TIPS CMOS technology for the first time as a most practical candidate for the 0.1 micrometer generation.
Unfortunately, it has reported that both the LDD and the LATID MOSFET (metal oxide semiconductor field effect transistor) structures are quite vulnerable to electrostatic discharge (ESD). The details of the ESD failures relating the device structures were disclosed in the investigation made by K. L. Chen ("Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors", in 1988 EOS/ESD Symposium Porceedings, p. 212). It is found that different device structures have different ESD failure threshold voltages. For the same dimension of NMOS transistors, the LDD transistor has the lowest ESD protection level when compared to DDD (double diffused drain) transistors. The high snapback voltage of these graded drain transistors, especially LDD transistors, has resulted in the ESD performance degradation. Although the DDD MOSFET device has a higher immunity to the ESD, it also shows a worse short channel effect as compared to the LDD or LATID MOSFET structures.